Exemplary embodiments of the present invention relate to method for fabricating a semiconductor device, and more particularly, to method for fabricating a MOS transistor and its neighboring patterns in a semiconductor device.
A circuit is first designed for implementing a designated function in a fabricating process of a semiconductor and subsequently, a lay-out drawing including a plurality of patterns and lines corresponding to the circuit is made.
An important issue in designing semiconductor technologies is the amount of semiconductor devices that may be implemented in one wafer. One semiconductor device fabricated in one wafer is called a die, and net dies signify how many dies are available in a wafer. Manufacturing cost can be reduced if net dies are increased in the wafer. Thus, designers try to reduce the size of the lay-out drawing. The size of transistors or lines in the lay-out drawing is typically implemented to the smallest sizes allowed by semiconductor technologies.
A MOS transistor in a semiconductor device includes a gate structure and a source/drain region neighboring the gate structure. The source or drain region electrically connects to a contact plug formed above the source or drain region. The gate structure comprises a dielectric layer and a conducting layer, which are stacked. The conducting layer typically includes a conducting silicon layer and a metal layer to raise the conducting layer's conductivity. Since each element of a MOS transistor is formed to the smallest size attainable, the contact plug on the source or drain region may be difficult to form. Considering a typical process of semiconductor technology, a dielectric layer is first formed on the gate structure and the source/drain region and subsequently, a contact hole is formed to expose the source/drain region by selectively etching the dielectric layer. A contact plug is formed to electrically connect with the source/drain region by filling the contact hole with a conducting material.
A design rule of semiconductor technology may be reduced. According to a design rule, fabricating the contact hole in the middle of a semiconductor fabricating process may be difficult. If the contact hole has a relatively wide thickness, a short may be formed between the gate structure and the contact. A short might cause the conducting layer of the gate structure to be easily exposed during a subsequent semiconductor fabrication process. If a sidewall between the gate structure and the contact plug has sufficient thickness, a process margin for making the contact hole may be very difficult to raise.